1 3.3 volt multimedia fifo 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, and 4,096 x 8 idt72v10081, idt72v11081 idt72v12081, idt72v13081 idt72v14081 ? 2003 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. dsc-6161/3 november 2003 idt and the idt logo are trademarks of integrated device technology, inc. industrial temperature ranges description the idt72v10081/72v11081/72v12081/72v13081/72v14081 devices are low-power first-in, first-out (fifo) memories with clocked read and write controls. these devices have a 256, 512, 1,024, 2,048 and 4,096 x 8-bit memory array, respectively. these fifos are applicable for a wide variety of data buffering needs such as graphics and interprocessor communication. these fifos have 8-bit input and output ports. the input port is controlled by a free-running clock (wclk) and write enable pin ( wen ). data is written into the multimedia fifo on every rising clock edge when the write enable pin is asserted. the output port is controlled by another clock pin (rclk) and read enable pin ( ren ). the read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. an output enable pin ( oe ) is provided on the read port for three-state control of the output. the multimedia fifos have two fixed flags, empty ( ef ) and full ( ff ). these fifos are fabricated using idt's submicron cmos technology. features ? ? ? ? ? 256 x 8-bit organization array (idt72v10081) ? ? ? ? ? 512 x 8-bit organization array (idt72v11081) ? ? ? ? ? 1,024 x 8-bit organization array (idt72v12081) ? ? ? ? ? 2,048 x 8-bit organization array (idt72v13081) ? ? ? ? ? 4,096 x 8-bit organization array (idt72v14081) ? ? ? ? ? 15 ns read/write cycle time ? ? ? ? ? 5v input tolerant ? ? ? ? ? independent read and write clocks ? ? ? ? ? empty and full flags signal fifo status ? ? ? ? ? output enable puts output data bus in high-impedance state ? ? ? ? ? available in 32-pin plastic thin quad flatpack (tqfp) ? ? ? ? ? industrial temperature range (?40 c to +85 c) functional block diagram reset logic flag outputs write control read control fifo array wclk wen d 0 - d 7 data in x8 rs ef q 0 - q 7 data out x8 rclk ren 6161 drw01 ff oe
2 idt72v10081/11081/12081/13081/14081 3.3v multimedia fifo 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 industrial temperature range symbol name i/o description d 0 -d 7 data inputs i data inputs for a 8-bit bus. ef empty flag o when ef is low, the fifo is empty and further data reads from the output are inhibited. when ef is high, the fifo is not empty. ef is synchronized to rclk. ff full flag o when ff is low, the fifo is full and further data writes into the input are inhibited. when ff is high, the fifo is not full. ff is synchronized to wclk. oe output enable i when oe is low, the data output bus is active. if oe is high, the output data bus will be in a high-impedance state. q 0 -q 7 data outputs o data outputs for a 8-bit bus. rclk read clock i data is read from the fifo on a low-to-high transition of rclk when ren is asserted. ren read enable i when ren is low, data is read from the fifo on every low-to-high transition of rclk. data will not be read from the fifo if the ef is low. rs reset i when rs is set low, internal read and write pointers are set to the first location of the ram array, ff goes high, and ef goes low. a reset is required before an initial write after power-up. wclk write clock i data is written into the fifo on a low-to-high transition of wclk when the write enable is asserted. wen write enable i when wen is low, data is written into the fifo on every low-to-high transition wclk. data will not be written into the fifo if the ff is low. v cc power i 3.3v volt power supply. gnd ground i ground pin. tqfp (pr32-1, order code: pf) top view pin configuration pin descriptions rs we n wclk v cc v cc q 1 q 2 q 3 5 6 7 8 16 d 6 gnd rclk gnd d 7 27 26 25 24 23 22 21 29 28 32 31 30 9 101112131415 d 5 gnd 6161 drw02 q 4 dnc (1) q 5 q 6 q 7 ef oe ff 1 2 3 4 20 19 18 17 index q 0 re n d 4 d 3 d 2 d 1 d 0 dnc (1) dnc (1) note: 1. dnc = do not connect.
3 idt72v10081/11081/12081/13081/14081 3.3v multimedia fifo 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 industrial temperature range idt72v10081 idt72v11081 idt72v12081 idt72v13081 idt72v14081 industrial t clk = 15 ns symbol parameter min. typ. max. unit i li (1) input leakage current (any input) ?1 ? 1 a i lo (2) output leakage current ?10 ? 10 a v oh output logic ?1? voltage, i oh = ?2ma 2.4 ? ? v v ol output logic ?0? voltage, i ol = 8ma ? ? 0.4 v i cc1 (3,4,5) active power supply current ? ? 20 ma i cc2 (3,6) standby current ? ? 5 ma capacitance (t a = +25 c, f = 1.0mhz) symbol parameter conditions max. unit c in (2) input capacitance v in = 0v 10 pf c out (1,2) output capacitance v out = 0v 10 pf notes: 1. with output deselected ( oe v ih ). 2. characterized values, not currently tested. dc electrical characteristics (industrial: v cc = 3.3v 0.3v, t a = -40 c to +85 c) notes: 1. measurements with 0.4 vin vcc. 2. oe v ih, 0.4 v out v cc . 3. tested with outputs disabled (i out = 0). 4. rclk and wclk toggle at 20 mhz and data inputs switch at 10 mhz. 5. typical i cc1 = 0.17 + 0.48*f s + 0.02*c l *f s (in ma) with v cc = 3.3v, t a = 25 c, f s = wclk frequency = rclk frequency (in mhz, using ttl levels), data switching at f s /2, c l = capacitive load (in pf). 6. all inputs = v cc - 0.2v or gnd + 0.2v, except rclk and wclk, which toggle at 20 mhz. absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v cc terminal only. symbol rating industrial unit v term (2) terminal voltage with ?0.5 to +5 v respect to gnd t stg storage temperature ?55 to +125 c i out dc output current ?50 to +50 ma recommended operating conditions symbol parameter min. typ. max. unit v cc supply voltage industrial 3.0 3.3 3.6 v gnd supply voltage 0 0 0 v v ih input high voltage industrial 2.0 ? 5.5 v v il input low voltage industrial -0.5 ? 0.8 v t a operating temperature -40 ? 85 c industrial
4 idt72v10081/11081/12081/13081/14081 3.3v multimedia fifo 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 industrial temperature range *includes jig and scope capacitances. ac test conditions in pulse levels gnd to 3.0v input rise/fall times 3ns input timing reference levels 1.5v output reference levels 1.5v output load see figure 1 or equivalent circuit figure 1. output load ac electrical characteristics (1) (industrial: v cc = 3.3 0.3v, ta = -40 c to + 85 c) notes: 1. pulse widths less than minimum values are not allowed. 2. values guaranteed by design, not currently tested. industrial idt72v10081l15 idt72v11081l15 idt72v12081l15 idt72v13081l15 idt72v14081l15 symbol parameter min. max. unit f s clock cycle frequency ? 66.7 m h z t a data access time 2 10 ns t clk clock cycle time 15 ? ns t clkh clock high time 6 ? ns t clkl clock low time 6 ? ns t ds data setup time 4 ? ns t dh data hold time 1 ? ns t ens enable setup time 4 ? ns t enh enable hold time 1 ? ns t rs reset pulse width (1) 15 ? ns t rss reset setup time 10 ? ns t rsr reset recovery time 10 ? ns t rsf reset to flag and output time ? 15 ns t olz output enable to output in low-z (2) 0?ns t oe output enable to output valid 3 8 ns t ohz output enable to output in high-z (2) 38ns t wff write clock to full flag ? 10 ns t ref read clock to empty flag ? 10 ns t skew1 skew time between read clock & write 6 ? ns clock for empty flag &full flag 30pf* 330 ? 3.3v 510 ? d.u.t. 6161 drw03
5 idt72v10081/11081/12081/13081/14081 3.3v multimedia fifo 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 industrial temperature range signal descriptions inputs data in (d0 - d7) data inputs for 8-bit wide data. controls reset ( rs ) reset is accomplished whenever the reset ( rs ) input is taken to a low state. during reset, both internal read and write pointers are set to the first location. a reset is required after power-up before a write operation can take place. the full flag ( ff ) will be reset to high after t rsf . the empty flag ( ef ) will be reset to low after t rsf . during reset, the output register is initialized to all zeros. write clock (wclk) a write cycle is initiated on the low-to-high transition of the write clock (wclk). data setup and hold times must be met in respect to the low-to-high transition of the write clock (wclk). the full flag (ff) is synchronized with respect to the low-to-high transition of the write clock (wclk). the write and read clocks can be asynchronous or coincident. write enable ( wen ) when write enable ( wen ) is low, data can be loaded into the input register and fifo array on the low-to-high transition of every write clock (wclk). data is stored in the fifo array sequentially and independently of any on-going read operation. to prevent data overflow, the full flag ( ff ) will go low, inhibiting further write operations. upon the completion of a valid read cycle, the full flag ( ff ) will go high after t wff , allowing a valid write to begin. write enable ( wen ) is ignored when the fifo is full. read clock (rclk) data can be read on the outputs on the low-to-high transition of the read clock (rclk). the empty flag ( ef )is synchronized with respect to the low- to-high transition of the read clock (rclk). the write and read clocks can be asynchronous or coincident. read enables ( ren ) when both read enable ( ren ) is low, data is read from the fifo array to the output register on the low-to-high transition of the read clock (rclk). when read enable ( ren ) is high, the output register holds the previous data and no new data is allowed to be loaded into the register. when all the data has been read from the fifo, the empty flag ( ef ) will go low, inhibiting further read operations. once a valid write operation has been accomplished, the empty flag ( ef ) will go high after t ref and a valid read can begin. the read enable ( ren ) is ignored when the fifo is empty. output enable ( oe ) when output enable ( oe ) is enabled (low), the parallel output buffers receive data from the output register. when output enable ( oe ) is disabled (high), the q output data bus is in a high-impedance state. outputs full flag ( ff ) the full flag ( ff ) will go low, inhibiting further write operation, when the device is full. if no reads are performed after reset ( rs ), the full flag ( ff ) will go low after 256 writes for the idt72v10081, 512 writes for the idt72v11081, 1,024 writes for the idt72v12081, 2,048 writes for the idt72v13081 and 4,096 writes for the idt72v14081. the full flag ( ff ) is synchronized with respect to the low-to-high transition of the write clock (wclk). empty flag ( ef ) the empty flag ( ef ) will go low, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating the device is empty. the empty flag ( ef ) is synchronized with respect to the low-to-high transition of the read clock (rclk). data outputs (q 0 - q7) data outputs for a 8-bit wide data.
6 idt72v10081/11081/12081/13081/14081 3.3v multimedia fifo 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 industrial temperature range notes: 1. after reset, the outputs will be low if oe = 0 and high-impedance if oe = 1. 2. the clocks (rclk, wclk) can be free-running during reset. figure 2. reset timing note: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge for ff to change during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then ff may not change state until the next wclk edge. figure 3. write cycle timing t rs t rsr rs ren t rsf t rsf oe = 1 oe = 0 (1) ef ff q 0 - q 7 6161 drw06 wen t rss t rsf t rsr t rss t dh t enh t skew1 (1) t clk t clkh t clkl t ds t wff t wff wclk d 0 - d 7 wen ff rclk ren no operation 6161 drw07 data in valid t ens
7 idt72v10081/11081/12081/13081/14081 3.3v multimedia fifo 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 industrial temperature range t ds d 0 (first valid write) t skew1 d 0 d 1 d 3 d 2 d 1 t ens t frl (1) t ref t a t olz t oe t a wclk d 0 - d 7 rclk ef ren q 0 - q 7 oe wen 6161 drw09 t ens note: 1. when t skew1 minimum specification, t frl = t clk + t skew1 when t skew1 < minimum specification, t frl = 2t clk + t skew1 or t clk + t skew1 the latency timings apply only at the empty boundary ( ef = low). figure 5. first data word latency timing t enh t ens no operation t olz valid data t skew1 (1) t clk t clkh t clkl t ref t ref t a t oe t ohz rclk ren ef q 0 - q 7 oe wclk wen 6161 drw08 note: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge for ef to change during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then ef may not change state until the next rclk edge. figure 4. read cycle timing
8 idt72v10081/11081/12081/13081/14081 3.3v multimedia fifo 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 industrial temperature range figure 7. empty flag timing figure 6. full flag timing t skew1 t ds t skew1 t enh t enh next data read data read wclk d 0 - d 7 ff wen rclk ren q 0 - q 7 t wff t wff t wff t ens t ens data in output register oe low no write no write 6161 drw10 t a t a t ens t ens (1) t enh no write t a t ds t ds data write 1 t ens t enh t ens t enh data write 2 wclk d 0 - d 7 rclk ef ren oe q 0 - q 7 data read t skew1 (1) t frl t ffl data in output register (1) t skew1 low t ref t ref t ref wen 6161 drw11 note: 1. when t skew1 minimum specification, t frl = t clk + t skew1 when t skew1 < minimum specification, t frl = 2t clk + t skew1 or t clk + t skew1 the latency timings apply only at the empty boundary ( ef = low).
9 corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-360-1753 san jose, ca 95138 fax: 408-284-2775 email: fifohelp@idt.com www.idt.com ordering information 6161 drw18 xxxxx idt device type x xx x x power speed package clock cycle time (t clk ) speed in nanoseconds process/ temperature range i industrial (-40 c to +85 c) pf plastic thin quad flatpack (tqfp, pr32-1) 72v10081 256 x 8 ? 3.3v multimedia fifo 72v11081 512 x 8 ? 3.3v multimedia fifo 72v12081 1,024 x 8 ? 3.3v multimedia fifo 72v13081 2,048 x 8 ? 3.3v multimedia fifo 72v14081 4,096 x 8 ? 3.3v multimedia fifo 15 industrial l low power datasheet document history 11/17/2003 pg. 1.
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